As dynamic random-access memory (DRAM) devices scale to smaller dimensions, an increasing emphasis is placed on patterning in forming three dimensional structures, including trenches for storage nodes as well as access transistors. In present day DRAM devices, transistors may be formed using narrow and tall semiconductor fin structures, often made from monocrystalline silicon. In present technology, a two-dimensional array of fin structures is formed by patterning a series of linear structures, where the linear structures are subsequently truncated using a chop mask. Because of the reduction in dimensions, misaligned chop mask may result in defective fin structures, while overlay tolerance is decreasing with each reduction in array pitch.
With respect to these and other considerations, the present disclosure is provided.